Energy area and speed optimized signal processing on FPGA

Matrix multiplication and Fast Fourier transform are two computational intensive DSP functions widely used as kernel operations in the applications such as graphics, imaging and wireless communication. Traditionally the performance metrics for signal processing has been latency and throughput. Energy efficiency has become increasingly important with proliferation of portable mobile devices as in software defined radio. A FPGA based system is a viable solution for requirement of adaptability and high computational power. But one limitation in FPGA is the limitation of resources. So there is need for optimization between energy, area and latency. There are numerous ways to map an algorithm to FPGA. So for the process of optimization the parameters must be determined by low level simulation of each of the designs possible which gives rise to vast time consumption. So there is need for a high level energy model in which parameters can be determined at algorithm and architectural level rather than low level simulation. In this dissertation matrix multiplication algorithms are implemented with pipelining and parallel processing features to increase throughput and reduce latency there by reduce the energy dissipation. But it increases area by the increased numbers of processing elements. The major area of the design is used by multiplier which further increases with increase in input word width which is difficult for VLSI implementation. So a word width decomposition technique is used with these algorithms to keep the size of multipliers fixed irrespective of the width of input data. FFT algorithms are implemented with pipelining to increase throughput. To reduce energy and area due to the complex multipliers used in the design for multiplication with twiddle factors, distributed arithmetic is used to provide multiplier less architecture. To compensate speed performance parallel distributed arithmetic models are used. This dissertation also proposes method of optimization of the parameters at high level for these two kernel applications by constructing a high level energy model using specified algorithms and architectures. Results obtained from the model are compared with those obtained from low level simulation for estimation of error

Design and FPGA Implementation of Channelizer & Frequency Hopping for Advanced SATCOM System

Advanced satellite communication systems should be capable of preventing unauthorized access or exploitation of communication services by adversaries. This can be achieved by use of wideband multi -channel digital transceivers which employ channelizer to extract the channel of interest from digitized RF bands for further baseband processing. Various anti-jamming techniques like Frequency hopping are used to prevent the systems from intentional jamming by the hostile systems. This paper presents an efficient channelizer architecture which supports wideband as well as narrowband channels with programmable channel bandwidth followed by frequency hopping for the proposed SATCOM system. The target design is a flexible channelization unit which divides the incoming data links of 11 MHz bandwidth into two data links in granularity of 0.5 MHz depending upon user requirements. First link is further sub-channelized into two sub-links each having a bandwidth of 25 KHz that is frequency hopped at a user programmable rate with desired random sequence. The same channelizer can be well applicablein any software defined radio receiver platforms due to flexibility of the design. Proposed design is tested on target hardware XilinxVirtex-IV FPGA xc4vsx35-10ff668. The design and implementation of the channelizer and frequency hopping technique arediscussed in detail